This invention generally pertains to design and development of digital integrated circuits and, more specifically, relates to methodologies for testing synchronization protocols using a digital simulator so as to ensure proper synchronization of signals crossing clock domain boundaries in an integrated circuit ultimately fabricated in accordance with a given design.
Digital integrated circuits continue to grow in density and complexity, as well as operating (clock) speed. With many thousands of gates on a single chip, early verification that a design will indeed provide its intended function has become an essential part of the design process. It is simply too costly xe2x80x94in delay and expense xe2x80x94to wait for xe2x80x9cfirst siliconxe2x80x9d to debug a complex digital design. Manual methods such as building and debugging a prototype circuit are not practical. Accordingly, electronic circuit designs are commonly subjected to computer software simulation prior to actual circuit manufacture. Prior to simulation, the proposed design is described using a hardware description language (xe2x80x9cHDLxe2x80x9d ). Various HDL""s are known, with Verilog and VHDL being perhaps the two leading examples.
A simulation process or simply xe2x80x9csimulatorxe2x80x9d is a computer program that xe2x80x9cexercisesxe2x80x9d or simulates operation of the design reflected in the HDL description. One well known simulator is Verilog-XL (Cadence Design Systems, Inc., San Jose, Calif.) The simulator exercises the design in response to a defined set of inputs or xe2x80x9ctest vectorsxe2x80x9d. Because of the sheer size and complexity of many designs, however, 100% testing of all possible logic states and dynamic events is simply not feasible. The test vectors are carefully designed (often using another software tool) in the hope of thoroughly exercising the hardware design to expose any errors or xe2x80x9cbugsxe2x80x9d.
In operation, the simulator sequentially assigns values to variables and applies simulated signals to elements in the hardware design. More specifically, the simulator steps through a sequence of instructions according to a virtual clock xe2x80x94the simulation time clock. The simulation time clock is a surrogate for an actual hardware clock (or clock input) that will drive the actual circuit. Thus, simulated processes defined as occurring at a first clock or simulation time are executed, giving rise to a first set of simulation results, e.g. signal value changes. Then the simulation time is incremented, and once again the various software processes necessary for modeling operation of the hardware design under simulation are executed, using the results of the previous simulation time. As the simulator steps through simulation time in this manner, variable values (modeling physical circuit signals) change and propagate through the circuit.
Many digital designs actually incorporate more than one clock signal. For example, a RISC core on an ASIC may require a first, relatively fast clock, while a memory block on the same chip uses a slower clock. Or, separate clocks of nominally the same frequency can be used to minimize noise. We refer to these different sections of logic as different xe2x80x9cclock domainsxe2x80x9d. It is generally necessary to synchronize the data or other signals to the receiving clock whenever signals or data is transferred between two different clock domains. This is conventionally done by providing two back-to-back flip-flop circuits in the receiving clock domain.
Normal zero delay simulation of such a system will work in a predictable manner since the metastability issues that can arise in a real flip-flop are not modeled. Furthermore, timing delays in the dual flip-flop synchronization element that could result in an extra clock being taken to synchronize the signal are also not modeled in a conventional digital simulator. This could lead to unforeseen bugs in the design of the synchronization logic.
FIG. 1 is a simplified schematic of a known synchronization element comprising a first flip flop 10 and a second flip flop 12. On a real device, such as an ASIC, a transition on the asynchronous signal input 14 could violate setup and hold time requirements on flip flop 10; which could result in the flip flop 10 clocking the previous value on its D input (14), rather then the new value, in response to the synchronizing clock signal 16. The new value at 14 would be clocked on the next subsequent clock 16 edge (assuming that the input 14 value had not changed in the interim), which would result in the circuit taking three clock (16) edges for the input to propagate to the output 18, rather than the normally expected value of only two clock edges. Consequently, an actual system that employs the synchronization scheme described may malfunction, even though the simulator does not detect an error.
The need remains, therefore, for improvements in HDL modeling and simulation techniques to overcome these digital simulator deficiencies. What is needed, more specifically, is a way to more vigorously test synchronization logic designs.
Another problem in the design and simulation of a digital circuit is that where a non-synchronized signal crosses from one clock domain to another clock domain, transitions in the signal can create timing violations on the receiving side. The synchronization protocol must ensure that these non-synchronized signals are sampled only when they are stable; yet bugs arising in this regard may be overlooked by the usual testing practices. The need remains therefore for improved methods of testing an asynchronous digital circuit design to reveal faults in the synchronization protocols.
In view of the foregoing background summary, it is an object of the present invention to overcome deficiencies in known simulation strategies in order to ensure that synchronization circuits will function as intended.
Another object of the invention is to provide an improved methodology for vigorously testing the design of synchronization logic in a digital design.
A further object of the invention is to ensure that during simulation of a digital design, signals that cross clock domain boundaries are sampled only when they are stable, i.e. when they satisfy timing constraints on the receiving side of the boundary.
According to one aspect of the invention, a circuit modelxe2x80x94more specifically a behavioral synchronization modelxe2x80x94is provided for emulating the variations to be expected in operation of an actual (physical) synchronization element. The circuit model is inserted into a digital design so that simulation of the modified design will expose the effects of variation in the number of clock cycles required by the corresponding synchronization element. The synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time exhibited in actual circuits. Preferably, the behavioral synchronization model is provided for each synchronization element in the design.
According to another aspect of the invention, a boundary behavioral module is provided for more rigorous testing of a design where an unsynchronized signal propagates from one clock domain to another. The boundary behavioral module is inserted into the signal path between the two clock domains so as to ensure that the signal is sampled only when it is stable, i.e. when the timing constraints of the receiving element are satisfied. Preferably, the behavioral synchronization module is provided at every net in the design where a signal traverses from one clock domain to another. Of course, the module is not physically inserted into an actual circuit; rather, it is incorporated into the design xe2x80x94more specifically into an HDL description of the design, for purposes of more accurately and thoroughly simulating operation of a circuit according to the design.
The behavioral module modifies the traversing signal so that it has at least one clock period (the receiving clock domain period) during which it has an xe2x80x9cXxe2x80x9d value. If this modified signal is sampled by the simulator while it has the xe2x80x9cXxe2x80x9d value, the xe2x80x9cXxe2x80x9d will quickly propagate through other logic and the simulation will fail. This mechanism guarantees that sampling of a signal from another clock domain is restricted by the design to a xe2x80x9csafexe2x80x9d window, and that sampling of the signal outside this window will cause simulation to fail; thus exposing the design bug.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment which proceeds with reference to the drawings.